I'm Schekeb Fateh

Abstract:We report an always-on event-driven asynchronous wake-up circuit with trainable pattern recognition capabilities to duty-cycle power-constrained internet-of-things (IoT) sensor nodes. The wake-up circuit is based on a level-crossing analog-to-digital converter (LC-ADC) employed as feature-extraction block with automatic activity-sampling rate scaling behavior. A novel asynchronous digital logic classifier for sequential pattern recognition is presented. It is driven by the LC-ADC activity and trained to minimize classification errors due to falsely detected events. As proof-of-concept, a prototype of the wake-up circuit is fabricated in 130nm CMOS technology within 0.054 mm2 of active area, covering up to 2.6 kHz of input signal bandwidth. The prototype has been first validated by interfacing it with a commercial accelerometer to classify hand gestures in real-time, reaching 81% of accuracy with only 2.2 µW at 1 V supply. To highlight the flexibility of the design, a second application, detecting pathologic ECG beats is also discussed.

Abstract: We report an asynchronous wake-up circuit with pattern recognition capabilities to duty-cycle biomedical SoCs in IoT healthcare applications. The wake up circuit is based on a LC-ADC to both reduce the number of samples and processing power. On-chip voltage references lower the overall system power consumption and reduce the number of external components. The circuit is highly configurable in order to be used in a set of diverse applications. A 130 nm CMOS prototype is demonstrated with pathological ECG with PVC, reaching 74.8% of accuracy with only 2.xn--1w-99b at 1V supply.

Abstract: We present ongoing work on a platform for mo- bile health (mHealth) and implantable telemetry devices with powerful point-of-contact processing capabilities based on our VivoSoC multi-sensor medical instrumentation system-on-chip (SoC), a custom power management IC, and only a few additional components – allowing the realisation of sub-cm3 devices. We detail the powerful yet efficient acquisition and parallel processing capabilities on the example of first applications, demonstrate system- and chip-level power management and address the application-layer considerations of a file system optimised for serial flash devices and job scheduling.

Abstract: We report a system-on-chip (SoC) realised in 130nm CMOS for implantable telemetry systems and mobile health ap- plications featuring 6 neural stimulation channels and acquisition circuits for 9× electrode-based recordings (ExG), 4×/32× photo- plethysmography (PPG), bio-impedance, and temperature. The SoC includes a low-power quad-core processor (38μW/MHz) with sophisticated power and clock management – enabling load-aware voltage scaling and selective clock-gating of single cores. The latter is demonstrated on the example of preliminary work on an implantable telemetry device for vital signs monitoring.

Abstract: The chip supports probes with up to 32 LEDs and 4 photodiodes and features a receiver that covers a wide input current range. A higher power-efficiency than the state-of-the-art results in 68% less total power consumption (incl. LEDs) for equal performance or 7dB higher performance at equal power consumption.

Abstract: In battery-powered medical instrumentation, the resolution and signal bandwidth of analog-to-digital converters (ADCs) have to be adapted to the needs of the application to avoid power wastage. This paper presents a reconfigurable successive approximation register (SAR) ADC implemented in 130 nm CMOS that resolves 5-14 bit with a maximum achievable effective number of bits (ENOB) of 13.5 using non-subtractive dither. In the proposed ADC design, the power consumption can be traded for accuracy to improve the energy efficiency and extend its application range, while reducing system integration complexity. A figure-of-merit (FoM) of 59 fJ/conversion is achieved at 1.2 V supply and the converter occupies an area of 0.42 mm2. Measurement results of the ADC integrated in a multi-channel analog front-end (AFE) circuit show the suitability of the ADC for portable medical monitoring devices.

Abstract: Multiple-input multiple-output (MIMO) technology is the key to meet the demands for data rate and link reliability of modern wireless communication systems, such as IEEE 802.11n or 3GPP-LTE. The full potential of MIMO systems can, however, only be achieved by means iterative MIMO decoding relying on soft-input soft-output (SISO) data detection. In this paper, we describe the first ASIC implementation of a SISO detector for iterative MIMO decoding. To this end, we propose a low-complexity minimum mean-squared error (MMSE) based parallel interference cancellation algorithm, develop a suitable VLSI architecture, and present a corresponding four-stream 1.5 mm2 detector chip in 90 nm CMOS technology. The fabricated ASIC includes all necessary preprocessing circuitry and exceeds the 600 Mb/s peak data-rate of IEEE 802.11n. A comparison with state-of-the-art MIMO-detector implementations demonstrates the performance benefits of our ASIC prototype in practical system-scenarios.